hardware, memory management (MMU, "Paged Memory Management
Unit", PMMU) A
hardware device or circuit that supports
the processor) is divided into
pages, whose size is 2^N,
(the offset within a page) are left unchanged. The upper
associatively) by the page number. Each page table entry
(PTE) gives the physical page number corresponding to the
virtual one. This is combined with the page offset to give
the complete physical address.
A PTE may also include information about whether the page has
It is possible that no physical memory (
RAM) has been
allocated to a given virtual page, in which case the MMU will
will then try to find a spare page of RAM and set up a new PTE
to map it to the requested virtual address. If no RAM is free
it may be necessary to choose an existing page, using some
"
paging"). There may also be a shortage of PTEs, in which
case the OS will have to free one for the new mapping.
architectures allow each process to have its own area or
configuration of the page table, with a mechanism to switch
between different mappings on a process switch. This means
that all processes can have the same virtual address space
rather than require load-time relocation.
After blocks of memory have been allocated and freed, the free
memory may become fragmented (discontinuous) so that the
largest contiguous block of free memory may be much smaller
range of virtual addresses can be mapped to several
non-contiguous blocks of physical memory.
In early designs memory management was performed by a separate
used with the
Zilog Z80 family of processors. Later CPUs
the same IC as the CPU.
(1999-05-24)